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Items where Author, Editor or other role is "Cadenas, Jose Oswaldo"

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Number of items: 11.

C

Cadenas, Jose O., Sherratt, Simon, Howlett, Des, Guy, Chris, Lundqvist, Karsten (2015) Virtualization for cost-effective teaching of assembly language programming. IEEE Transactions on Education, 58 (4). pp. 282-288. ISSN 0018-9359. E-ISSN 1557-9638. (doi:10.1109/TE.2015.2405895) (KAR id:57352)
[thumbnail of Teaching ARM assembly language without a hardware kit and yet running a live Linux system with an ARM processor with all software development tools available for free]
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Cadenas, Jose O., Sherratt, Robert Simon, Huerta, Pablo, Kao, Wen-Chung, Megson, Graham M. (2013) C-slow retimed parallel histogram architectures for consumer imaging devices. IEEE Transactions on Consumer Electronics, 59 (2). pp. 291-295. ISSN 0098-3063. (doi:10.1109/TCE.2013.6531108) (KAR id:57359)
[thumbnail of Not in the format with the publisher]
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Cadenas, J.O., Sherratt, R. Simon, Huerta, P. (2011) Parallel pipelined histogram architectures. Electronics Letters, 47 (20). pp. 1118-1120. ISSN 0013-5194. (doi:10.1049/el.2011.2390) (KAR id:57370)
[thumbnail of This is not in the published template found in the actual journal]
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L

Laszuk, Dawid, Cadenas, Jose O., Nasuto, Slawomir J. (2016) EMD performance comparison: single vs double floating points. International journal of signal processing systems, 4 (4). pp. 349-353. ISSN 2315-4535. (doi:10.18178/ijsps.4.4.349-353) (KAR id:57350)
[thumbnail of Laszuk2015 EMD performance SFP vs DFP.pdf]
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Laszuk, Dawid, Cadenas, Jose O., Nasuto, Slawomir J. (2016) On the Phase Coupling of Two Components Mixing in Empirical Mode Decomposition. Advances in Data Science and Adaptive Analysis, 8 (1). Article Number 1650004. ISSN 2424-922X. E-ISSN 2424-9238. (doi:10.1142/S2424922X16500042) (KAR id:57663)
[thumbnail of ws-aada.pdf]
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M

Medina, Jose Cadenas (2015) Pipelined median architecture. Electronics Letters, 51 (24). pp. 1999-2001. ISSN 0013-5194. (doi:10.1049/el.2015.1898) (KAR id:57351)
[thumbnail of Latest improvement to non-sorting methods for computing the median suitable for hardware architectures]
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Medina, Jose Cadenas, Megson, G. M., Sherratt, Simon (2015) Median architecture by accumulative parallel counters. IEEE Transactions on Circuits and Systems II, Express Briefs, 62 (7). pp. 661-665. ISSN 1549-7747. E-ISSN 1558-3791. (doi:10.1109/TCSII.2015.2415655) (KAR id:57353)
[thumbnail of Improvements on computing the median suitable for hardware architecture]
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Medina, Jose Cadenas, Megson, G. M. (2014) Rapid preconditioning of data for accelerating convex hull algorithms. Electronics Letters, 50 (4). pp. 270-272. ISSN 0013-5194. E-ISSN 1350-911X. (doi:10.1049/el.2013.3507) (KAR id:57356)
[thumbnail of ELLPolyline-R6.pdf]
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Megson, G.M., Cadenas, J.O., Sherratt, R.S., Huerta, P., Kao, W.C. (2013) A parallel quantum histogram architecture. IEEE Transactions on Circuits and Systems II, Express Briefs, 60 (7). pp. 437-441. ISSN 1549-7747. E-ISSN 1558-3791. (doi:10.1109/TCSII.2013.2258263) (KAR id:57358)
[thumbnail of Not in the final format with the publisher]
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Medina, Oswaldo Cadenas, Megson, G. M., Sherratt, Simon, Huerta, P. (2012) Fast median calculation method. Electronics Letters, 48 (10). pp. 558-560. ISSN 0013-5194. E-ISSN 1350-911X. (doi:10.1049/el.2012.0343) (KAR id:57365)
[thumbnail of Computing the median without sorting suitable for fast hardware architectures]
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O

Oswaldo, José, Megson, Graham M., Hendriks, Cris L. Luengo (2016) Preconditioning 2D integer data for fast convex hull computations. PLoS ONE, 11 (3). Article Number 149860. ISSN 1932-6203. (doi:10.1371/journal.pone.0149860) (KAR id:57349)
[thumbnail of Fast method to pre-process 2D integer data points before applying any convex hull algorithm; doing this accelerates the overall process.]
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This list was generated on Fri Jan 21 19:40:52 2022 GMT.