Median architecture by accumulative parallel counters

Medina, Jose Cadenas and Megson, G. M. and Sherratt, Simon (2015) Median architecture by accumulative parallel counters. IEEE Transactions on Circuits and Systems II, Express Briefs, 62 (7). pp. 661-665. ISSN 1549-7747. E-ISSN 1558-3791. (doi: (Full text available)

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The time to process each of W/B processing blocks of a median calculation method on a set of N W-bit integers is improved here by a factor of three compared to the literature. Parallelism uncovered in blocks containing B-bit slices are exploited by independent accumulative parallel counters so that the median is calculated faster than any known previous method for any N, W values. The improvements to the method are discussed in the context of calculating the median for a moving set of N integers for which a pipelined architecture is developed. An extra benefit of smaller area for the architecture is also reported.

Item Type: Article
Uncontrolled keywords: Median Filter, Pipelined Processing, Image Processing.
Subjects: Q Science > QA Mathematics (inc Computing science) > QA 75 Electronic computers. Computer science
T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800 Electronics (see also: telecommunications) > TK7874 Microelectronics
Divisions: Faculties > Sciences > School of Engineering and Digital Arts
Faculties > Sciences > School of Engineering and Digital Arts > Instrumentation, Control and Embedded Systems
Depositing User: Jose Oswaldo Cadenas
Date Deposited: 23 Sep 2016 06:54 UTC
Last Modified: 05 Oct 2016 09:39 UTC
Resource URI: (The current URI for this page, for reference purposes)
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