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A parallel quantum histogram architecture

Megson, G.M., Cadenas, J.O., Sherratt, R.S., Huerta, P., Kao, W.C. (2013) A parallel quantum histogram architecture. IEEE Transactions on Circuits and Systems II, Express Briefs, 60 (7). pp. 437-441. ISSN 1549-7747. E-ISSN 1558-3791. (doi:10.1109/TCSII.2013.2258263) (KAR id:57358)

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A parallel formulation of an algorithm for the histogram computation of n data items using an on-the-fly data decomposition and a novel quantum-like representation (QR) is developed. The QR transformation separates multiple data read operations from multiple bin update operations thereby making it easier to bind data items into their corresponding histogram bins. Under this model the steps required to compute the histogram is n/s + t steps, where s is a speedup factor and t is associated with pipeline latency. Here, we show that an overall speedup factor, s, is available for up to an eightfold acceleration. Our evaluation also shows that each one of these cells requires less area/time complexity compared to similar proposals found in the literature.

Item Type: Article
DOI/Identification number: 10.1109/TCSII.2013.2258263
Uncontrolled keywords: Histogram, parallel architectures, parallel algorithms, quantum representation.
Subjects: T Technology > TK Electrical engineering. Electronics. Nuclear engineering > TK7800 Electronics > TK7874 Microelectronics. Integrated circuits
Divisions: Divisions > Division of Computing, Engineering and Mathematical Sciences > School of Engineering and Digital Arts
Depositing User: Jose Oswaldo Cadenas
Date Deposited: 05 Oct 2016 08:13 UTC
Last Modified: 16 Nov 2021 10:23 UTC
Resource URI: (The current URI for this page, for reference purposes)

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