Parallel pipelined histogram architectures

Cadenas, J.O. and Sherratt, R. Simon and Huerta, P. (2011) Parallel pipelined histogram architectures. Electronics Letters, 47 (20). pp. 1118-1120. ISSN 0013-5194. (doi:https://doi.org/10.1049/el.2011.2390) (Full text available)

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http://dx.doi.org/10.1049/el.2011.2390

Abstract

Proposed is a unique cell histogram architecture which will process k data items in parallel to compute 2q histogram bins per time step. An array of m/2q cells computes an m-bin histogram with a speed-up factor of k; k ? 2 makes it faster than current dual-ported memory implementations. Furthermore, simple mechanisms for conflict-free storing of the histogram bins into an external memory array are discussed.

Item Type: Article
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800 Electronics (see also: telecommunications) > TK7880 Applications of electronics (inc industrial & domestic) > TK7885 Computer engineering
T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800 Electronics (see also: telecommunications) > TK7880 Applications of electronics (inc industrial & domestic) > TK7895.E42 Embedded Systems
Divisions: Faculties > Sciences > School of Engineering and Digital Arts
Faculties > Sciences > School of Engineering and Digital Arts > Instrumentation, Control and Embedded Systems
Depositing User: Jose Oswaldo Cadenas
Date Deposited: 05 Oct 2016 08:04 UTC
Last Modified: 06 Oct 2016 13:22 UTC
Resource URI: https://kar.kent.ac.uk/id/eprint/57370 (The current URI for this page, for reference purposes)
Cadenas, J.O.: https://orcid.org/0000-0003-4152-6458
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