Pipelined median architecture

Medina, Jose Cadenas (2015) Pipelined median architecture. Electronics Letters, 51 (24). pp. 1999-2001. ISSN 0013-5194. (doi:10.1049/el.2015.1898)

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http://dx.doi.org/10.1049/el.2015.1898

Abstract

The core processing step of the noise reduction median filter technique is to find the median within a window of integers. A four-step procedure method to compute the running median of the last N W-bit stream of integers showing area and time benefits is proposed. The method slices integers into groups of B-bit using a pipeline of W/B blocks. From the method, an architecture is developed giving a designer the flexibility to exchange area gains for faster frequency of operation, or vice versa, by adjusting N, W and B parameter values. Gains in area of around 40%, or in frequency of operation of around 20%, are clearly observed by FPGA circuit implementations compared to latest methods in the literature.

Item Type: Article
DOI/Identification number: 10.1049/el.2015.1898
Uncontrolled keywords: median, pipeline
Subjects: Q Science > QA Mathematics (inc Computing science) > QA 75 Electronic computers. Computer science
T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800 Electronics (see also: telecommunications) > TK7874 Microelectronics
Divisions: Faculties > Sciences > School of Engineering and Digital Arts
Faculties > Sciences > School of Engineering and Digital Arts > Instrumentation, Control and Embedded Systems
Depositing User: Jose Oswaldo Cadenas
Date Deposited: 23 Sep 2016 07:12 UTC
Last Modified: 29 May 2019 17:51 UTC
Resource URI: https://kar.kent.ac.uk/id/eprint/57351 (The current URI for this page, for reference purposes)
Medina, Jose Cadenas: https://orcid.org/0000-0003-4152-6458
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