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C-slow retimed parallel histogram architectures for consumer imaging devices

Cadenas, Jose O., Sherratt, Robert Simon, Huerta, Pablo, Kao, Wen-Chung, Megson, Graham M. (2013) C-slow retimed parallel histogram architectures for consumer imaging devices. IEEE Transactions on Consumer Electronics, 59 (2). pp. 291-295. ISSN 0098-3063. (doi:10.1109/TCE.2013.6531108) (KAR id:57359)

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A parallel pipelined array of cells suitable for real-time computation of histograms is proposed. The cell architecture builds on previous work obtained via C-slow retiming techniques and can be clocked at 65 percent faster frequency than previous arrays. The new arrays can be exploited for higher throughput particularly when dual data rate sampling techniques are used to operate on single streams of data from image sensors. In this way, the new cell operates on a p-bit data bus which is more convenient for interfacing to camera sensors or to microprocessors in consumer digital cameras.

Item Type: Article
DOI/Identification number: 10.1109/TCE.2013.6531108
Uncontrolled keywords: Parallel Histograms, Pipelined Array, FPGA, Digital Imaging, Image Processing.
Subjects: T Technology > TK Electrical engineering. Electronics. Nuclear engineering > TK7800 Electronics > TK7880 Applications of electronics
Divisions: Divisions > Division of Computing, Engineering and Mathematical Sciences > School of Engineering and Digital Arts
Depositing User: Jose Oswaldo Cadenas
Date Deposited: 05 Oct 2016 08:28 UTC
Last Modified: 16 Nov 2021 10:23 UTC
Resource URI: (The current URI for this page, for reference purposes)
Cadenas, Jose O.:
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