Medina, Jose Cadenas, Megson, G. M., Sherratt, Simon (2015) Median architecture by accumulative parallel counters. IEEE Transactions on Circuits and Systems II, Express Briefs, 62 (7). pp. 661-665. ISSN 1549-7747. E-ISSN 1558-3791. (doi:10.1109/TCSII.2015.2415655) (KAR id:57353)
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PDF (Improvements on computing the median suitable for hardware architecture)
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| Official URL: http://dx.doi.org/10.1109/TCSII.2015.2415655 |
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Abstract
The time to process each of W/B processing blocks of a median calculation method on a set of N W-bit integers is improved here by a factor of three compared to the literature. Parallelism uncovered in blocks containing B-bit slices are exploited by independent accumulative parallel counters so that the median is calculated faster than any known previous method for any N, W values. The improvements to the method are discussed in the context of calculating the median for a moving set of N integers for which a pipelined architecture is developed. An extra benefit of smaller area for the architecture is also reported.
| Item Type: | Article |
|---|---|
| DOI/Identification number: | 10.1109/TCSII.2015.2415655 |
| Uncontrolled keywords: | Median Filter, Pipelined Processing, Image Processing. |
| Subjects: |
Q Science > QA Mathematics (inc Computing science) > QA 75 Electronic computers. Computer science T Technology > TK Electrical engineering. Electronics. Nuclear engineering > TK7800 Electronics > TK7874 Microelectronics. Integrated circuits |
| Institutional Unit: | Schools > School of Engineering, Mathematics and Physics > Engineering |
| Former Institutional Unit: |
Divisions > Division of Computing, Engineering and Mathematical Sciences > School of Engineering and Digital Arts
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| Depositing User: | Jose Oswaldo Cadenas |
| Date Deposited: | 23 Sep 2016 06:54 UTC |
| Last Modified: | 20 May 2025 10:41 UTC |
| Resource URI: | https://kar.kent.ac.uk/id/eprint/57353 (The current URI for this page, for reference purposes) |
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https://orcid.org/0000-0003-4152-6458
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