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Hanna, Keith (1998) Automatic Verification of Mixed-Level Logic Circuits. In: Gopalakrishna, O. and Windley, P., eds. Formal Methods in Computer-Aided Design. Lecture Notes in Computer Science , 1522. pp. 133-148. Springer-Verlag, Berlin, Proceedings FMCAS 98 ISBN 3-540-65191-8. (doi:10.1007/3-540-49519-3_10) (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided) (KAR id:21573)
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