Automatic Verification of Mixed-Level Logic Circuits

Hanna, Keith (1998) Automatic Verification of Mixed-Level Logic Circuits. In: Formal Methods in Computer-Aided Design. (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided)

The full text of this publication is not available from this repository. (Contact us about this Publication)
Official URL


An approach is described to the specification and verification of digital systems implemented wholly or partly at the analog level of abstraction. The approach relies upon specifying the behaviours of analog components (such as transistors) by piecewise-linear predicates on voltages and currents. A decision procedure is described that can, for a wide class of specifications, automatically establish the correctness of an implementation.

Item Type: Conference or workshop item (Paper)
Subjects: Q Science > QA Mathematics (inc Computing science) > QA 76 Software, computer programming,
Divisions: Faculties > Science Technology and Medical Studies > School of Computing > Theoretical Computing Group
Depositing User: Mark Wheadon
Date Deposited: 26 Aug 2009 18:05
Last Modified: 26 Aug 2009 18:05
Resource URI: (The current URI for this page, for reference purposes)
  • Depositors only (login required):


Downloads per month over past year