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Automatic Verification of Mixed-Level Logic Circuits

Hanna, Keith (1998) Automatic Verification of Mixed-Level Logic Circuits. In: Gopalakrishna, O. and Windley, P., eds. Formal Methods in Computer-Aided Design. Lecture Notes in Computer Science , 1522. pp. 133-148. Springer-Verlag, Berlin, Proceedings FMCAS 98 ISBN 3-540-65191-8. (doi:10.1007/3-540-49519-3_10) (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided)

The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided. (Contact us about this Publication)
Official URL
http://dx.doi.org/10.1007/3-540-49519-3_10

Abstract

An approach is described to the specification and verification of digital systems implemented wholly or partly at the analog level of abstraction. The approach relies upon specifying the behaviours of analog components (such as transistors) by piecewise-linear predicates on voltages and currents. A decision procedure is described that can, for a wide class of specifications, automatically establish the correctness of an implementation.

Item Type: Conference or workshop item (Paper)
DOI/Identification number: 10.1007/3-540-49519-3_10
Subjects: Q Science > QA Mathematics (inc Computing science) > QA 76 Software, computer programming,
Divisions: Faculties > Sciences > School of Computing > Theoretical Computing Group
Depositing User: Mark Wheadon
Date Deposited: 26 Aug 2009 18:05 UTC
Last Modified: 28 May 2019 14:01 UTC
Resource URI: https://kar.kent.ac.uk/id/eprint/21573 (The current URI for this page, for reference purposes)
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