The Impact of Modern FPGA Architectures on Neural Hardware: A Case Study of the TOTEM Neural Processor

McBader, Stephanie and Lee, Peter and Sartori, Alvise (2004) The Impact of Modern FPGA Architectures on Neural Hardware: A Case Study of the TOTEM Neural Processor. In: 2004 IEEE International Joint Conference on Neural Networks. IEEE International Joint Conference on Neural Networks (IJCNN) . IEEE, pp. 3149-3154. ISBN 0-7803-8359-1. (doi:10.1109/IJCNN.2004.1381178) (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided) (KAR id:8697)

The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided.
Official URL: http://dx.doi.org/10.1109/IJCNN.2004.1381178

Abstract

The implementation of neural processors in hardware is a very challenging task. However, recent advances in programmable architectures facilitate this task by providing the fundamental hardware blocks for building neural structures. Using the TOTEM neural processor as a case study, this paper reports on the main advantages of implementing neural hardware on programmable logic devices such as FPGAs.

Item Type:	Book section
DOI/Identification number:	10.1109/IJCNN.2004.1381178
Uncontrolled keywords:	field programmable gate arrays; hardware; computer aided software engineering; computer architecture; neurons; registers; read-write memory; signal processing algorithms; arithmetic; parallel processing
Subjects:	T Technology > TK Electrical engineering. Electronics. Nuclear engineering > TK7800 Electronics
Divisions:	Divisions > Division of Computing, Engineering and Mathematical Sciences > School of Engineering and Digital Arts
Depositing User:	Yiqing Liang
Date Deposited:	16 Aug 2009 19:48 UTC
Last Modified:	05 Nov 2024 09:41 UTC
Resource URI:	https://kar.kent.ac.uk/id/eprint/8697 (The current URI for this page, for reference purposes)

University of Kent Author Information

Lee, Peter.

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