Paschalakis, Stavros and Lee, Peter (2003) Double Precision Floating-Point Arithmetic on FPGAs. In: 2003 IEEE International Conference on Field-Programmable Technology. IEEE, pp. 352-358. ISBN 0-7803-8320-6. (doi:10.1109/FPT.2003.1275775) (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided) (KAR id:7583)
The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided. | |
Official URL: http://dx.doi.org/10.1109/FPT.2003.1275775 |
Abstract
We present low cost FPGA floating-point arithmetic circuits for all the common operations, i.e. addition/subtraction, multiplication, division and square root. Such circuits can be extremely useful in the FPGA implementation of complex systems that benefit from the reprogrammability and parallelism of the FPGA device but also require a general purpose arithmetic unit. While previous work has considered circuits for low precision floating-point formats, we consider the implementation of 64-bit double precision circuits that also provide rounding and exception handling.
Item Type: | Book section |
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DOI/Identification number: | 10.1109/FPT.2003.1275775 |
Uncontrolled keywords: | floating-point arithmetic; field programmable gate arrays; circuits; electronics packaging; parallel processing; signal processing algorithms; costs; hardware; computer vision; application software |
Subjects: | T Technology > TK Electrical engineering. Electronics. Nuclear engineering > TK7800 Electronics |
Divisions: | Divisions > Division of Computing, Engineering and Mathematical Sciences > School of Engineering and Digital Arts |
Depositing User: | Yiqing Liang |
Date Deposited: | 04 Aug 2009 08:33 UTC |
Last Modified: | 05 Nov 2024 09:39 UTC |
Resource URI: | https://kar.kent.ac.uk/id/eprint/7583 (The current URI for this page, for reference purposes) |
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