Howard, D, Walczowski, Les T., Waller, Winston A.J., Smith, M.H. (1990) Generation of Ordered Sub-circuits for an Automatic Sizing Program. IEE Proceedings G: Circuits Devices and Systems, 7 (4). pp. 43-44. ISSN 0956-3768. (doi:10.1049/ip-g-2.1990.0048) (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided) (KAR id:49999)
| The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided. | |
| Official URL: https://doi.org/10.1049/ip-g-2.1990.0048 |
Abstract
The design of increasingly complex integrated circuits requires synthesis tools rather than analysis tools. A tool that calculates transistor sizes is useful both to design a new circuit and to move an existing design to another process. The paper describes an algorithm that can be used in such a program to structure an otherwise unstructured array of unsized transistors in a CMOS digital circuit. This structure is related to the functionality of the circuit, so that the sizing model is provided with all the information required. The paper then goes on to discuss how the `subcircuits' were ordered so that they could be sized, taking the necessary factors into account
| Item Type: | Article |
|---|---|
| DOI/Identification number: | 10.1049/ip-g-2.1990.0048 |
| Subjects: | T Technology |
| Divisions: | Divisions > Division of Computing, Engineering and Mathematical Sciences > School of Engineering and Digital Arts |
| Depositing User: | Tina Thompson |
| Date Deposited: | 03 Aug 2015 10:52 UTC |
| Last Modified: | 05 Nov 2024 10:35 UTC |
| Resource URI: | https://kar.kent.ac.uk/id/eprint/49999 (The current URI for this page, for reference purposes) |
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