Moser, Steve, Lee, Peter, Podoleanu, Adrian G.H. (2015) An FPGA Architecture for Extracting Real-Time Zernike Coefficients from Measured Phase Gradients. Measurement Science Review, 15 (2). pp. 92-100. E-ISSN 1335-8871. (doi:10.1515/msr-2015-0014) (KAR id:48966)
PDF (An FPGA Architecture for Extracting Real-Time Zernike Coefficients from Measured Phase Gradients)
Publisher pdf
Language: English
This work is licensed under a Creative Commons Attribution-NoDerivatives 4.0 International License.
|
|
Download this file (PDF/499kB) |
Preview |
Request a format suitable for use with assistive technology e.g. a screenreader | |
Official URL: http://dx.doi.org/10.1515/msr-2015-0014 |
Abstract
Zernike modes are commonly used in adaptive optics systems to represent optical wavefronts. However, real-time calculation of Zernike modes is time consuming due to two factors: the large factorial components in the radial polynomials used to define them and the large inverse matrix calculation needed for the linear fit. This paper presents an efficient parallel method for calculating Zernike coefficients from phase gradients produced by a Shack-Hartman sensor and its real-time implementation using an FPGA by pre-calculation and storage of subsections of the large inverse matrix. The architecture exploits symmetries within the Zernike modes to achieve a significant reduction in memory requirements and a speed-up of 2.9 when compared to published results utilising a 2D-FFT method for a grid size of 8×8. Analysis of processor element internal word length requirements show that 24-bit precision in precalculated values of the Zernike mode partial derivatives ensures less than 0.5% error per Zernike coefficient and an overall error of <1%. The design has been synthesized on a Xilinx Spartan-6 XC6SLX45 FPGA. The resource utilisation on this device is <3% of slice registers, <15% of slice LUTs, and approximately 48% of available DSP blocks independent of the Shack-Hartmann grid size. Block RAM usage is <16% for Shack-Hartmann grid sizes up to 32×32.
Item Type: | Article |
---|---|
DOI/Identification number: | 10.1515/msr-2015-0014 |
Uncontrolled keywords: | Singular value decomposition; field programmable gate array |
Subjects: | T Technology |
Divisions: |
Divisions > Division of Computing, Engineering and Mathematical Sciences > School of Engineering and Digital Arts Divisions > Division of Natural Sciences > Physics and Astronomy |
Depositing User: | Tina Thompson |
Date Deposited: | 09 Jun 2015 13:10 UTC |
Last Modified: | 05 Nov 2024 10:33 UTC |
Resource URI: | https://kar.kent.ac.uk/id/eprint/48966 (The current URI for this page, for reference purposes) |
- Link to SensusAccess
- Export to:
- RefWorks
- EPrints3 XML
- BibTeX
- CSV
- Depositors only (login required):