Dynamic scaling scheme for hardware-accelerated edge detection

Many real-time signal and image processing algorithms require extensive usage of floating-point arithmetic, which is very complex in implementation and resource intensive in hardware. However, faster and less complex fixed-point solutions do not provide the needed accuracy for selected applications Therefore, i n this paper, an optimised dynamic scaling fixed-point process is suggested and implemented. The solution is tested for edge detection in polarimetric synthetic aperture radar (POLSAR) data, i.e. data with a very high dynamic range, and compare with an implementation using floating-point arithmetic. In summary, the dynamic scaling scheme provides a fast solution while preserving high accuracy. Using ModelSim to examine the performance, the proposed architecture operates four times faster than the original implementation-using a third of the original hardware resources. The accuracy was maintained at a high level, with the difference in output values of less than one for most of the cases. Index Terms— Dynamic scaling, fixed-point, floating point, r eal-time embedded system, field programmable gate arrays.

DYNAMIC SCALING SCHEME FOR HARDWARE-ACCELERATED EDGE DETECTION (PDF Download Available). Available from: http://www.researchgate.net/publication/275037301_DYNAMIC_SCALING_SCHEME_FOR_HARDWARE-ACCELERATED_EDGE_DETECTION [accessed Sep 2, 2015].