Kuo, S, McLoughlin, Ian Vince, Mehrotra, K (2003) Reconfigurable processing framework for space-time block codes. In: , Australian Telecommunications, Networks and Applications Conference. . (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided) (KAR id:48806)
The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided. |
Abstract
Space-time block coding has emerged in recent years as a promising research topic to enable future high-speed wireless communications networks and services. A considerable number of authors have developed algorithms and techniques that have been explored in simulations. However, fully implemented systems are rare. This paper considers the use of reconfigurable logic for implementing space-time block coding algorithms, allowing greater coding complexity than traditional DSP implemented systems. In particular, a number of matrix multiplication-style architectures are proposed for implementing channel estimators on FPGA hardware. These are compared in terms of speed and size, and accuracy is compared with a MATLAB simulation.
Reconfigurable processing framework for space-time block codes (PDF Download Available). Available from: http://www.researchgate.net/publication/228991771_Reconfigurable_processing_framework_for_space-time_block_codes [accessed Sep 4, 2015].
Item Type: | Conference or workshop item (Paper) |
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Additional information: | Unmapped bibliographic data: Y1 - 2003/// [EPrints field already has value set] |
Subjects: | T Technology |
Divisions: | Divisions > Division of Computing, Engineering and Mathematical Sciences > School of Computing |
Depositing User: | Ian McLoughlin |
Date Deposited: | 04 Sep 2015 13:04 UTC |
Last Modified: | 05 Nov 2024 10:32 UTC |
Resource URI: | https://kar.kent.ac.uk/id/eprint/48806 (The current URI for this page, for reference purposes) |
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