Hardware architecture for data concealment using sub-band coding, LSB coding and pseudo-random bit stream generators

Adi, R.W. and Tio, C.M.M and McLoughlin, Ian Vince (2000) Hardware architecture for data concealment using sub-band coding, LSB coding and pseudo-random bit stream generators. In: 2000 TENCON Proceedings. Intelligent Systems and Technologies for the New Millennium. IEEE, pp. 221-225. ISBN 0-7803-6355-8. (doi:10.1109/TENCON.2000.892261) (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided) (KAR id:48760)

The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided.
Official URL: http://dx.doi.org/10.1109/TENCON.2000.892261

Abstract

Data concealment using LSB coding is a simple algorithm for hiding data within audio. This paper firstly extends the algorithm to alleviate frequency offset effects, then applies the technique to a multi-rate filterbank, and reports the results of a VLSI implementation for the system. The architecture has been designed to give real time performance and consequently has high efficiency, whilst maintaining audio fidelity through careful analysis of wordlength and other effects. In this paper, we also consider the feasibility of the selected implementation approach

Item Type:	Book section
DOI/Identification number:	10.1109/TENCON.2000.892261
Additional information:	Unmapped bibliographic data: Y1 - 2000/// [EPrints field already has value set] LA - English [Field not mapped to EPrints]
Uncontrolled keywords:	Clocks, Computer architecture, DAT, Data encapsulation, Data engineering, Filters, Hardware, LSB coding, Logic, Performance analysis, Process design, VLSI, VLSI implementation, Very large scale integration, algorithm, amplifier, analogue input/output, audio coding, audio data hiding, audio equipment, audio fidelity, audio precision analyser, copy protection, data concealment, digital audio input/output, hardware architecture, performance, pipeline processing, pipelined architecture, pseudo-random bit stream generators, real time performance, sub-band coding, system parameters estimation, unauthorised copying, wordlength
Subjects:	T Technology
Divisions:	Divisions > Division of Computing, Engineering and Mathematical Sciences > School of Computing
Depositing User:	Ian McLoughlin
Date Deposited:	27 Aug 2015 11:29 UTC
Last Modified:	05 Nov 2024 10:32 UTC
Resource URI:	https://kar.kent.ac.uk/id/eprint/48760 (The current URI for this page, for reference purposes)

University of Kent Author Information

McLoughlin, Ian Vince.

Creator's ORCID:	https://orcid.org/0000-0001-7111-2008
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