An Evaluation of Intel's Restricted Transactional Memory for CPAs

Ritson, Carl G. and Barnes, Frederick R.M. (2013) An Evaluation of Intel's Restricted Transactional Memory for CPAs. In: Welch, Peter H. and Barnes, Frederick R.M. and Broenink, Jan F. and Chalmers, Kevin and Pedersen, Jan B. and Sampson, Adam T., eds. Communicating Process Architectures 2013. Open Channel Publishing pp. 271-291. ISBN 978-0-9565409-7-3. (Full text available)

Abstract

With the release of their latest processor microarchitecture, codenamed Haswell, Intel added new Transactional Synchronization Extensions (TSX) to their processors' instruction set. These extensions include support for Restricted Transactional Memory (RTM), a programming model in which arbitrary sized units of memory can be read and written in an atomic manner. This paper describes the low-level RTM programming model, benchmarks the performance of its instructions and speculates on how it may be used to implement and enhance Communicating Process Architectures.

Item Type:	Conference or workshop item (Paper)
Uncontrolled keywords:	Transactional Synchronization Extensions, TSX, Restricted Transactional Memory, RTM, transactional memory, performance
Subjects:	Q Science > QA Mathematics (inc Computing science) > QA 76 Software, computer programming,
Divisions:	Faculties > Sciences > School of Computing > Programming Languages and Systems Group
Depositing User:	F. Barnes
Date Deposited:	27 Nov 2013 04:44 UTC
Last Modified:	10 Feb 2014 15:44 UTC
Resource URI:	https://kar.kent.ac.uk/id/eprint/36939 (The current URI for this page, for reference purposes)