Anzellotti, G., Battiti, Roberto, Lazzizzera, I., Soncini, G., Zorat, Alessandro, Sartori, Alvise, Tecchiolli, Giampietro, Lee, Peter (1995) Totem:. a Highly Parallel Chip for Triggering Applications with Inductive Learning Based on the Reactive Tabu Search. International Journal of Modern Physics C, 6 (4). pp. 555-560. ISSN 0129-1831. (doi:10.1142/S0129183195000423) (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided) (KAR id:19673)
The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided. | |
Official URL: http://dx.doi.org/10.1142/S0129183195000423 |
Abstract
The training of a Multi-Layer Perceptron (MLP) classifier is considered as a Combinatorial Optimization task and solved using the Reactive Tabu Search (RTS) method. RTS needs only forward passes (no derivatives) and does not require high precision network parameters. TOTEM, a special-purpose VLSI chip, was developed to take advantage of the limited memory and processing requirements of RTS: the final system effects a very close match between hardware and training algorithm. The RTS algorithm and the design of TOTEM are discussed, together with the operational characteristics of the VLSI chip and some preliminary training and generalization tests on triggering tasks.
Item Type: | Article |
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DOI/Identification number: | 10.1142/S0129183195000423 |
Uncontrolled keywords: | high energy physics; triggering; inductive learning; special purpose processors |
Subjects: | Q Science > QA Mathematics (inc Computing science) > QA 75 Electronic computers. Computer science |
Divisions: | Divisions > Division of Computing, Engineering and Mathematical Sciences > School of Computing |
Depositing User: | P. Ogbuji |
Date Deposited: | 08 Jun 2009 18:40 UTC |
Last Modified: | 05 Nov 2024 09:56 UTC |
Resource URI: | https://kar.kent.ac.uk/id/eprint/19673 (The current URI for this page, for reference purposes) |
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