Rapid layout synthesis for analog VLSI

Walczowski, Les T. and Waller, Winston A.J. and Nalbantis, D. and Shibayama, Katsuyuki (1996) Rapid layout synthesis for analog VLSI. In: 3rd IEEE International Conference on Electronics, Circuits, and Systems (ICECS 96), Rhodes, Greece. (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided)

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A technology independent synthesis system which rapidly generates the layout of analog VLSI circuits has been developed. Based on a specification of a circuit's required performance and the target process, design rule correct layout is generated. The complete system has been tested by synthesizing op-amps in the CMOS and bipolar domains. Comparison of the specification with results of simulating the circuit extracted from the synthesized layout, show that the system is accurate to within a few per cent for most parameters.

Item Type: Conference or workshop item (Other)
Subjects: Q Science > Q Science (General)
Divisions: Faculties > Science Technology and Medical Studies > School of Engineering and Digital Arts
Depositing User: P. Ogbuji
Date Deposited: 30 Apr 2009 18:12
Last Modified: 11 Jun 2014 09:58
Resource URI: https://kar.kent.ac.uk/id/eprint/18564 (The current URI for this page, for reference purposes)
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