Walczowski, Les T., Waller, Winston A.J., Nalbantis, D. (1996) Rapid layout synthesis for analog VLSI. In: ICECS 96 - Proceedings of the Third IEEE International Conference on Electonics, Circuits, and Systems. 1-2. pp. 378-381. IEEE ISBN 0-7803-3650-X. (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided) (KAR id:18564)
| The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided. |
Abstract
A technology independent synthesis system which rapidly generates the layout of analog VLSI circuits has been developed. Based on a specification of a circuit's required performance and the target process, design rule correct layout is generated. The complete system has been tested by synthesizing op-amps in the CMOS and bipolar domains. Comparison of the specification with results of simulating the circuit extracted from the synthesized layout, show that the system is accurate to within a few per cent for most parameters.
| Item Type: | Conference or workshop item (Other) |
|---|---|
| Subjects: | Q Science > Q Science (General) |
| Divisions: | Divisions > Division of Computing, Engineering and Mathematical Sciences > School of Engineering and Digital Arts |
| Depositing User: | P. Ogbuji |
| Date Deposited: | 30 Apr 2009 18:12 UTC |
| Last Modified: | 16 Nov 2021 09:56 UTC |
| Resource URI: | https://kar.kent.ac.uk/id/eprint/18564 (The current URI for this page, for reference purposes) |
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