Some aspects of adaptive logic for pattern recognition

This thesis deals with pattern recognizers (PRs) which are adaptive and amenable to hardware realization. Such PRs consist of networks of microcircuit modules (SLAMs: Stored-Logic Adaptive Microcircuits) which are used as feature extractors and which ensure a high throughput by their parallel operation.

Previous workers have adopted the. number of training patterns as a measure for training such PRs on different pattern classes. In this thesis, the number of memory bits set in the SLAMs is considered instead, and this is shown to provide a better balance between sections of the PRs called discriminators.

Simulations are carried out to observe how the size of the PR and the amount of training affect the performance and a quantitative comparison with a template matching classifier is presented. The effect of clustering the SLAM inputs within the input matrix is also investigated and PRs with SLAMs which have their outputs weighted according to their memory contents are also simulated.

From the results, a technique to optimize the performance of the PRs is proposed and a possible development of the SLAM module is suggested.