McBader, Stephanie and Lee, Peter (2003) Reducing Memory Bottlenecks in Embedded, Parallel Image Processors. IEE Electronics Letters, 39 (1). pp. 33-35. ISSN 0013-5194. (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided)
Owing to the sequential nature of memory interfaces, as well as the growing processor-memory performance gap, the design of parallel image processors is often faced with a challenge in deciding memory organisation and distribution. This work addresses the problem of memory access bottlenecks in parallel digital image processors and presents one solution which demonstrates up to 93.4% reduction over standard sequential methods.
|Subjects:||T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800 Electronics (see also: telecommunications)|
|Divisions:||Faculties > Science Technology and Medical Studies > School of Engineering and Digital Arts > Instrumentation, Control and Embedded Systems|
|Depositing User:||Yiqing Liang|
|Date Deposited:||15 Sep 2008 10:22|
|Last Modified:||23 Jun 2014 09:26|
|Resource URI:||https://kar.kent.ac.uk/id/eprint/7622 (The current URI for this page, for reference purposes)|