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FLAG: A Framework for FPGA Based Load Generator in Profinet Communication

Khalid, Ahmad, Saha, Sangeet, Bhatt, Bina, Gu, Dongbing, Howells, Gareth, McDonald-Maier, Klaus D. (2019) FLAG: A Framework for FPGA Based Load Generator in Profinet Communication. In: International Conference on Industry 4.0 and Artificial Intelligence Technologies, 19-22 Aug 2019, Cambridge, UK. (Unpublished) (Access to this publication is currently restricted. You may be able to access a copy if URLs are provided) (KAR id:74065)

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Abstract

Like other automated system technologies, PROFINET, a real-time Industrial Ethernet Standard has shown increasing level of integration into the present IT Infrastructure. Such vast use of PROFINET can expose the controllers and I/O devices to operate in critical failures when traffic goes unexpectedly higher than normal. Rigorous testing of the running devices then becomes essential and therefore, in this paper, we prototype and design an FPGA based load Generating solution called “FLAG (FPGA based LoAd Generator) for PROFINET based traffic at the desired load configurations such as, bits per second, the number and size of the packets with their Ethertypes and MAC addresses. We have employed, a Zynq-7000 FPGA as our implementation platform for the proposed FLAG framework. The system can easily be deployed and accessed via the web or command line interface for successful load generation. Extensive experiments have been conducted to verify the effectiveness of our proposed solution and the results confirm that the proposed framework is capable to generate precise load at Fast/Gigabit line rate with a defined number of packets.

Item Type: Conference or workshop item (Paper)
Projects: INCASE
Uncontrolled keywords: Profinet, FPGA, NetJury, load generation
Subjects: Q Science > QA Mathematics (inc Computing science) > QA 76 Software, computer programming, > QA76.76 Computer software
T Technology > TK Electrical engineering. Electronics. Nuclear engineering > TK7800 Electronics > TK7874 Microelectronics. Integrated circuits
Divisions: Divisions > Division of Computing, Engineering and Mathematical Sciences > School of Engineering and Digital Arts
Funders: Organisations -1 not found.
Depositing User: Gareth Howells
Date Deposited: 22 May 2019 14:35 UTC
Last Modified: 23 Jan 2023 16:56 UTC
Resource URI: https://kar.kent.ac.uk/id/eprint/74065 (The current URI for this page, for reference purposes)

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