Towards a Twofold Approach to the Verification of Generated VHDL Systems

Akehurst, David H. and Wood, Stephen K. and Howells, Gareth and McDonald-Maier, Klaus D. (2007) Towards a Twofold Approach to the Verification of Generated VHDL Systems. In: International Workshop on MODEASY, in conjunction with Forum on Specificatin and Design Languages (FDL 07), 2007 September, Barcelona, Spain. (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided)

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The rise of Model Driven Development, Domain Specific Languages and Generative Programming as new techniques for systems and software engineering means that the actual code that is compiled and executed is no longer written by a human, it is generated by a tool. To give confidence that the desired system has been generated, it is necessary to provide a successful means to verify the generated code. This paper proposes a twofold approach to verification, drawing on techniques from both the testing and formal approaches to verification. The concepts are discussed in the context of generating VHDL code from a UML State Machine.

Item Type: Conference or workshop item (Paper)
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800 Electronics (see also: telecommunications),
Divisions: Faculties > Science Technology and Medical Studies > School of Engineering and Digital Arts > Image and Information Engineering
Depositing User: Yiqing Liang
Date Deposited: 14 Aug 2008 15:27
Last Modified: 23 May 2014 09:29
Resource URI: (The current URI for this page, for reference purposes)
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