Coherence Gated Laser Ray Tracing Based on a High Speed FPGA Platform

eld, rendering them incapable of differentiating light returned from targets with many layers (such as the human retina). Instead, the measured wavefront is the superposition of the wavefronts returned from each layer. By combining principles from low-coherence interferometry and wavefront sensing, a depth-resolved wavefront sensor may be realised. This allows only light from within the coherence-gate of the interferometer to be measured by the wavefront sensing device. By adjusting the axial position of the coherence-gate, wavefronts from distinct layers of a multi-layer object may be measured. This method has been demonstrated for the Shack-Hartmann wavefront sensor but requires an external PC for image processing and wavefront reconstruction.

This dissertation presents, for the first time, a depth-resolved laser ray tracing wavefront sensor. Results are shown, in the form of Zernike modes, which demonstrate the ability of the instrument to resolve wavefronts from a multi-layer target (two stacked microscope slides and a mirror). Also, an FPGA based embedded system was developed for all command, control, image processing and wavefront reconstruction functions.

This highly specialised system is able to perform these operations in real-time, limited

only by the frame rate of the available camera. Specfic attention is given to the portion of the system focused on wavefront reconstruction. Zernike modes are commonly used in adaptive optics systems to represent

optical wavefronts. However, real-time calculation of Zernike modes is time consuming due to two factors: the large factorial components in the radial polynomials used to define them, and the large inverse matrix calculation needed for the linear t. This dissertation presents an efficient parallel method for calculating Zernike coefficients from phase gradients and its real-time implementation using an FPGA by pre-calculation

and storage of subsections of the large inverse matrix. The architecture exploits symmetries within the Zernike modes to achieve a significant reduction in memory requirements and a speed-up of 2.9 when compared to published results utilising a 2D-FFT method for a grid size of 8 x 8. Analysis of the processor element's internal word length requirements show that 24-bit precision in pre-calculated values of the Zernike

mode partial derivatives ensures less than 0.5% error per Zernike coefficient and an overall error of less than 1%. The design has been synthesized on a X