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Implementation and Applications of Logarithmic Signal Processing on an FPGA

Chaudhary, Mandeep (2016) Implementation and Applications of Logarithmic Signal Processing on an FPGA. Doctor of Philosophy (PhD) thesis, University of Kent. (KAR id:55184)

Language: English
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This thesis presents two novel algorithms for converting a normalised binary floating point number into a binary logarithmic number with the single-precision of a floating point number. The thesis highlights the importance of logarithmic number systems in real-time DSP applications. A real-time cross-correlation application where logarithmic signal processing is used to simplify the complex computation is presented.

The first algorithm presented in this thesis comprises two stages. A piecewise linear approximation to the original logarithmic curve is performed in the first stage and a scaled-down normalised error curve is stored in the second stage. The algorithm requires less than 20 kbits of ROM and a maximum of three small multipliers. The architecture is implemented on Xilinx's Spartan3 and Spartan6 FPGA family. Synthesis results confirm that the algorithm operates at a frequency of 42.3 MHz on a Spartan3 device and 127.8 MHz on a Spartan6. Both solutions have a pipeline latency of two clocks. The operating speed increases to 71.4 MHz and 160 MHz respectively when the pipeline latencies increase to eight clocks.

The proposed algorithm is further improved by using a PWL (Piece-Wise Linear) approximation of the transform curve combined with a PWL approximation of a scaled version of the normalized segment error. A hardware approach for reducing the memory with additional XOR gates in the second stage is also presented. The architecture presented uses just one 18k bit Block RAM (BRAM) and synthesis results indicate operating frequencies of 93 and 110 MHz when implemented on the Xilinx Spartan3 and Spartan6 devices respectively.

Finally a novel prototype of an FPGA-based four channel correlation velocimetry system is presented. The system operates at a higher sampling frquency than previous published work and outputs the new result after every new sample it receives. The system works at a sampling frequency of 195.31 kHz and a sample resolution of 12 bits. The prototype system calculates a delay in a range of 0 to 2.6 ms with a resolution of 5.12 us.

Item Type: Thesis (Doctor of Philosophy (PhD))
Thesis advisor: Lee, Peter
Uncontrolled keywords: Computer arithmetic, function evaluation, piecewise linear approximation, table-based methods, uniform segmentation, Electrostatic sensors, Field programmable gate arrays, Signal processing, Sensor systems and applications and Computer Arithmetic.
Subjects: T Technology > TA Engineering (General). Civil engineering (General) > TA168 Systems engineering
Divisions: Divisions > Division of Computing, Engineering and Mathematical Sciences > School of Engineering and Digital Arts
Depositing User: Users 1 not found.
Date Deposited: 28 Apr 2016 13:00 UTC
Last Modified: 11 Dec 2022 01:28 UTC
Resource URI: (The current URI for this page, for reference purposes)

University of Kent Author Information

Chaudhary, Mandeep.

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