A method for sizing transistors in CMOS op-amps

Smith, M.H., Walczowski, Les T., Waller, Winston A.J., Howard, D. (1991) A method for sizing transistors in CMOS op-amps. In: IEEE International Symposium on Circuits & Systems. . pp. 2016-2019. (doi:10.1109/ISCAS.1991.176061) (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided)

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Official URL
http://dx.doi.org/10.1109/ISCAS.1991.176061

Abstract

The authors present a method for automatically calculating the size of the transistors and passive components in a CMOS op-amp given the specification and loading of the op-amp. The method is similar to that used in the OASYS program in that it uses no simulation. Like the OASYS method, the authors estimate the sizes and then calculate the parasitics. The parasitics calculated are then used to recalculate the sizes. This process continues until the parasitics change only little. Unlike OASYS, the authors separated the sizing method from the model of the transistor. This means one is able to use any transistor model to size the transistors, and, because the method does not use simulation and so makes less calls of the model equations, the model used can be more complicated than that used for simulation

Item Type: Conference or workshop item (Paper)
DOI/Identification number: 10.1109/ISCAS.1991.176061
Subjects: T Technology
Divisions: Faculties > Sciences > School of Engineering and Digital Arts
Faculties > Sciences > School of Engineering and Digital Arts > Digital Media
Depositing User: Tina Thompson
Date Deposited: 30 Jul 2015 14:07 UTC
Last Modified: 29 May 2019 14:57 UTC
Resource URI: https://kar.kent.ac.uk/id/eprint/49916 (The current URI for this page, for reference purposes)
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