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FPGA implementation of space-time block coding systems

Baghaie, M. and Kuo, S. and McLoughlin, Ian Vince (2004) FPGA implementation of space-time block coding systems. In: Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication. IEEE, pp. 591-594. ISBN 0-7803-7938-1. (doi:10.1109/CASSET.2004.1321957) (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided)

The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided. (Contact us about this Publication)
Official URL
http://dx.doi.org/10.1109/CASSET.2004.1321957

Abstract

In this paper, the implementation of space-time block coding systems is discussed, particularly through the use of programmable logic such as FPGAs. The rationale for choice of such devices in preference to DSPs is discussed followed by an analysis of the design and development process and the methodologies employed in the design process. An example space-time system, time-reversal space-time block coding (TR-STBC) is discussed and implementation described.

Item Type: Book section
DOI/Identification number: 10.1109/CASSET.2004.1321957
Additional information: Unmapped bibliographic data: Y1 - 2004/// [EPrints field already has value set]
Uncontrolled keywords: field programmable gate arrays; block codes; digital signal processing; space technology; logic devices; programmable logic arrays; programmable logic devices; process design; hardware; clocks
Subjects: T Technology
Divisions: Faculties > Sciences > School of Computing
Depositing User: Ian McLoughlin
Date Deposited: 04 Sep 2015 13:10 UTC
Last Modified: 02 Aug 2019 14:47 UTC
Resource URI: https://kar.kent.ac.uk/id/eprint/48779 (The current URI for this page, for reference purposes)
McLoughlin, Ian Vince: https://orcid.org/0000-0001-7111-2008
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