16-Bit Clocked Adiabatic Logic (CAL) Leading One Detector for a Logarithmic Signal Processor

Yemiscioglu, Gurtac and Lee, Peter (2012) 16-Bit Clocked Adiabatic Logic (CAL) Leading One Detector for a Logarithmic Signal Processor. In: Ph.D. Research in Microelectronics and Electronics (PRIME), 2012 8th Conference, 12-15 June 2012, Aachen, Germany. (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided)

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Abstract

This paper describes the architecture of a Leading- One Detector (LOD) and its implementation using Clocked Adiabatic Logic (CAL). This modular circuit has been designed for use in a 16-bit logarithmic signal processor but can easily be adapted for longer or shorter word lengths. The circuit can also be used as the first stage in a floating-point converter. It has been designed using an AMS 0.35 micrometer CMOS process and consumes an area of 0.02 mm2. Spice simulations have shown that the circuit can operate at frequencies up to 250 MHz and energy calculation have indicated 20.38 pJ power consumption at the maximum operating frequency.

Item Type: Conference or workshop item (Paper)
Subjects: T Technology
Divisions: Faculties > Sciences > School of Engineering and Digital Arts
Faculties > Sciences > School of Engineering and Digital Arts > Instrumentation, Control and Embedded Systems
Depositing User: Tina Thompson
Date Deposited: 01 Nov 2013 14:04 UTC
Last Modified: 23 Jun 2014 09:28 UTC
Resource URI: https://kar.kent.ac.uk/id/eprint/35921 (The current URI for this page, for reference purposes)
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