An FPGA based Digital Lock-In Amplifier Implemented using MFIR Resonators

Vandenbussche, Jean-Jacques, Lee, Peter, Peuteman, Joan (2012) An FPGA based Digital Lock-In Amplifier Implemented using MFIR Resonators. In: Signal Processing, Pattern Recognition and Applications / 779: Computer Graphics and Imaging - 2012, June 18-20 2012, Crete, Greece. (doi:10.2316/P.2012.778-034) (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided)

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Official URL
http://dx.doi.org/10.2316/P.2012.778-034

Abstract

This paper presents an alternative architecture for a digital lock-in amplifier that uses a linear phase digital low pass resonator built with a Multiplicative Finite Impulse Response (MFIR) filter. The paper compares the performance of the new architecture with traditional implementations that have been described in the literature. It shows that the MFIR resonator has a superior performance due to its very small equivalent noise bandwidth. The system has been implemented and tested on a Xilinx Spartan3A DSP Field Programmable Gate Array (FPGA). The paper also shows that the MFIR filter only uses a small amount of slices which makes it perfectly suited for implementation in state of the art mid-range FPGA’s.

Item Type: Conference or workshop item (Paper)
DOI/Identification number: 10.2316/P.2012.778-034
Subjects: T Technology
Divisions: Faculties > Sciences > School of Engineering and Digital Arts
Faculties > Sciences > School of Engineering and Digital Arts > Instrumentation, Control and Embedded Systems
Depositing User: Tina Thompson
Date Deposited: 01 Nov 2013 13:59 UTC
Last Modified: 29 May 2019 11:14 UTC
Resource URI: https://kar.kent.ac.uk/id/eprint/35919 (The current URI for this page, for reference purposes)
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