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16-Bit Clocked Adiabatic Logic (CAL) logarithmic signal processor

Yemiscioglu, Gurtac, Lee, Peter (2012) 16-Bit Clocked Adiabatic Logic (CAL) logarithmic signal processor. In: 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS). . pp. 113-116. IEEE ISBN 978-1-4673-2526-4. E-ISBN 978-1-4673-2525-7. (doi:10.1109/MWSCAS.2012.6291970) (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided)

The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided. (Contact us about this Publication)
Official URL
http://dx.doi.org/10.1109/MWSCAS.2012.6291970

Abstract

This paper describes a 16-bit Logarithmic Signal Processor and its implementation using Clocked Adiabatic Logic (CAL). The proposed architectures for Lin2Log and Log2Lin converters are based on a linear interpolation algorithm. The CAL-Logarithmic Signal Processor has been designed using an AMS 0.35 μm CMOS process and consumes an area of 7.3 μm 2 . Spice simulations have shown that the circuit can operate at frequencies up to 250MHz and energy calculation have indicated 211.34 pJ power consumption at the maximum operating frequency.

Item Type: Conference or workshop item (Paper)
DOI/Identification number: 10.1109/MWSCAS.2012.6291970
Uncontrolled keywords: clocks; read only memory; energy dissipation; layout; computer architecture; signal processing algorithms; energy loss
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Faculties > Sciences > School of Engineering and Digital Arts > Instrumentation, Control and Embedded Systems
Depositing User: P.S.P. Yapp
Date Deposited: 29 Oct 2013 16:25 UTC
Last Modified: 23 Jul 2019 08:43 UTC
Resource URI: https://kar.kent.ac.uk/id/eprint/35785 (The current URI for this page, for reference purposes)
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