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Two-stage logarithmic converter with reduced memory requirements

Chaudhary, Mandeep, Lee, Peter (2013) Two-stage logarithmic converter with reduced memory requirements. IET Computers & Digital Techniques, 8 (1). pp. 23-29. ISSN 1751-8601. E-ISSN 1751-861X. (doi:10.1049/iet-cdt.2012.0134) (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided) (KAR id:35524)

The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided.
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This study presents an efficient method for converting a normalised binary number x (1 ? x < 2) into a binary logarithm. The algorithm requires less memory and fewer arithmetic components to achieve 23 bits of fractional precision than other algorithms using uniform and non-uniform piecewise linear or piecewise polynomial techniques and requires less than 20 kbits of ROM and a maximum of three multipliers. It is easily extensible to higher numeric precision and has been implemented on Xilinx Spartan3 and Spartan6 field programmable gate arrays (FPGA) to show the effect of recent architectural enhancements to the reconfigurable fabric on implementation efficiency. Synthesis results confirm that the algorithm operates at a frequency of 42.3 MHz on a Spartan3 device and 127.8 MHz on a Spartan6 with a latency of two clocks. This increases to 71.4 and 160 MHz, respectively, when the latency is increased to eight clocks. On a Spartan6 XC6SLX16 device, the converter uses just 55 logic slices, three multipliers and 11.3kbits of Block RAM configured as ROM.

Item Type: Article
DOI/Identification number: 10.1049/iet-cdt.2012.0134
Uncontrolled keywords: Inspec keywords: read-only storage; piecewise linear techniques; field programmable gate arrays; piecewise polynomial techniques; convertors; digital arithmetic; reconfigurable architectures Other keywords: arithmetic components; ROM; Xilinx Spartan6 FPGA; nonuniform piecewise polynomial techniques; frequency 42.3 MHz; logic slices; frequency 127.8 MHz; reconflgurable fabric; block RAM; nonuniform piecewise linear techniques; Spartan6 XC6SLX16 device; reduced memory requirements; numeric precision; multipliers; frequency 71.4 MHz; Xilinx Spartan3 FPGA; uniform piecewise linear techniques; fractional precision; binary logarithm; storage capacity 11.3 Kbit; normalised binary number conversion; uniform piecewise polynomial techniques; frequency 160 MHz; two-stage logarithmic converter Subjects: Computer architecture; Memory circuits; Logic circuits; Semiconductor storage; Digital arithmetic methods; Logic and switching circuits; Convertors
Subjects: T Technology
Divisions: Divisions > Division of Computing, Engineering and Mathematical Sciences > School of Engineering and Digital Arts
Depositing User: Tina Thompson
Date Deposited: 18 Oct 2013 14:08 UTC
Last Modified: 16 Nov 2021 10:12 UTC
Resource URI: (The current URI for this page, for reference purposes)
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