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Controlled Timed Petri Nets: Equivalence Relations, Model Reduction

Boel, R. and Bordbar, B. and Stremersch, G. (1998) Controlled Timed Petri Nets: Equivalence Relations, Model Reduction. In: SMC'98 Conference Proceedings. 1998 IEEE International Conference on Systems, Man, and Cybernetics. IEEE Systems, Man, and Cybernetics, Conference, 1 . IEEE, pp. 674-679. ISBN 0-7803-4778-1. (doi:10.1109/ICSMC.1998.725491) (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided)

The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided. (Contact us about this Publication)
Official URL
http://dx.doi.org/ 10.1109/ICSMC.1998.725491

Abstract

Discusses controlled timed Petri net models for the formal synthesis of supervisory controllers for real time discrete event systems (e.g. communication protocols, supervisors for FMSs, control of batch processes). We extend the standard Petri net formalism with firing delays between the time a transition becomes state enabled, and the time it is executed. These firing delays are partly controllable between lower and upper bounds. The goal is to guarantee that certain forbidden distributions of tokens will never occur. For this purpose we define the influencing net corresponding to forbidden sets. Deciding whether a maximally permissive controller exists, and if yes, constructing such a controller, requires solving large sets of linear inequalities over firing times in this influencing net. This is generally a very large set. Hence we study some equivalence relations between different subnets of a timed Petri net. An example shows that replacing a subnet by a simpler equivalent subnet can significantly reduce the size of the sets of inequalities to be solved.

Item Type: Book section
DOI/Identification number: 10.1109/ICSMC.1998.725491
Uncontrolled keywords: petri nets; reduced order systems; communication system control; control system synthesis; real time systems; discrete even systems; protocols; process control; delay effects; upper bound
Subjects: Q Science > QA Mathematics (inc Computing science) > QA 76 Software, computer programming,
Divisions: Faculties > Sciences > School of Computing > Systems Architecture Group
Faculties > Sciences > School of Computing > Theoretical Computing Group
Depositing User: Mark Wheadon
Date Deposited: 26 Aug 2009 17:13 UTC
Last Modified: 23 Jul 2019 14:14 UTC
Resource URI: https://kar.kent.ac.uk/id/eprint/21596 (The current URI for this page, for reference purposes)
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