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A C-Testable Parallel Multipler Using Differencial Casecode Voltage Swish (DCVS) Logic

Waller, Winston A.J. and Aziz, S.M. (1994) A C-Testable Parallel Multipler Using Differencial Casecode Voltage Swish (DCVS) Logic. In: Yanagawa, T. and Ivey, P.A., eds. VLSI 93 - IFIP Transactions A. Computer Science and Technology. North Holland, pp. 133-142. ISBN 0-444-89911-1. (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided)

The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided. (Contact us about this Publication)

Abstract

In this paper, a new C-testable design of a parallel multiplier is presented. It is based on the well known modified Booth's algorithm which reduces the number of partial products by a factor of two compared to the straightforward iterative array multiplier. The multiplier is implemented using the highly testable clocked Differential Cascode Voltage Switch (DCVS) logic. It requires only 21 test vectors to detect all detectable single stuck-at, stuck-on and stuck-open faults. Compared to a non-C-testable DCVS design, it requires only 6 extra inputs, 2 extra outputs and a small amount of extra logic which is also self-checking.

Item Type: Book section
Subjects: Q Science > QA Mathematics (inc Computing science) > QA 75 Electronic computers. Computer science
Divisions: Faculties > Sciences > School of Computing > Theoretical Computing Group
Depositing User: P. Ogbuji
Date Deposited: 09 Jun 2009 16:51 UTC
Last Modified: 28 May 2019 13:58 UTC
Resource URI: https://kar.kent.ac.uk/id/eprint/20093 (The current URI for this page, for reference purposes)
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