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A hardware FPGA implementation of a 2-D median filter using a novel rank adjustment technique

Swenson, R.L. and Dimond, Keith R. (1999) A hardware FPGA implementation of a 2-D median filter using a novel rank adjustment technique. In: Seventh International Conference on Image Processing And Its Applications, 1999. IEEE, pp. 103-106. ISBN 0-85296-717-9. (doi:10.1049/cp:19990290) (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided)

The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided. (Contact us about this Publication)
Official URL
http://dx.doi.org/10.1049/cp:19990290

Abstract

This paper presents the design and implementation on a Field Programmable Gate Array (FPGA) of a 2-D median filter, which is capable of obtaining a median value every clock cycle. The device is designed to operate in rear-time with rates of over 80 megasamples per second on n-bit sample sequences. Also, the operation speed remains constant regardless of the size of the selected mask N.

Item Type: Book section
DOI/Identification number: 10.1049/cp:19990290
Additional information: Proceedings Paper; Issue: 465
Uncontrolled keywords: hardware FPGA implementation; 2D median filter; rank adjustment technique; design; implementation; field programmable gate array; real-time; n-bit sequences; operation speed; mask
Subjects: Q Science > Q Science (General) > Q335 Artificial intelligence
Q Science > QA Mathematics (inc Computing science) > QA 76 Software, computer programming,
T Technology > TA Engineering (General). Civil engineering (General)
Divisions: Faculties > Sciences > School of Engineering and Digital Arts
Depositing User: F.D. Zabet
Date Deposited: 23 Mar 2009 18:09 UTC
Last Modified: 09 Aug 2019 10:28 UTC
Resource URI: https://kar.kent.ac.uk/id/eprint/16659 (The current URI for this page, for reference purposes)
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