Testing Ethernet Networks for the ATLAS Data Collection System

This paper reports recent work on Ethernet traffic generation and analysis. We use Gigabit Ethernet NICs running customized embedded software and custom-built 32-port Fast Ethernet boards based on FPGAs to study the behavior of large Ethernet networks. The traffic generation software is able to accommodate many traffic distributions with the ultimate goal of generating traffic that resembles the data collection system of the ATLAS experiment at CERN. Each packet is time stamped with a global clock value and therefore we are able to compute an accurate measure of the network latency. Various other information collected from the boards is displayed in real time on a graphical interface. This work provides the tools to study a test bed representing a fraction of the 1600 ATLAS detector readout buffers and 600 Level 2 trigger CPUs using a combination of Fast Ethernet boards and the Gigabit Ethernet NICs.