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Testing Differential Split-Level CMOS Circuits

Aziz, S.M., Waller, Winston A.J. (1994) Testing Differential Split-Level CMOS Circuits. IEE Proceedings: Circuits, Devices and Systems, 141 (6). pp. 451-456. ISSN 1350-2409. (doi:10.1049/ip-cds:19941524) (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided) (KAR id:20366)

The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided.
Official URL:
http://dx.doi.org/10.1049/ip-cds:19941524

Abstract

The paper addresses the problem of testing differential split-level (DSL) CMOS circuits. The behaviour of DSL circuits under single stuck-at, stuck-on and stuck-open faults is analysed. It is shown that most of these faults in DSL circuits cannot be deterministically tested by logic monitoring. However, the presence of any of these faults results in an increase in the steady state power supply current in the circuit when the fault is sensitised. A testing technique based on differential supply current monitoring to detect these faults in DSL integrated circuits is presented.

Item Type: Article
DOI/Identification number: 10.1049/ip-cds:19941524
Uncontrolled keywords: TESTABILITY ANALYSIS; DESIGN FOR TESTABILITY; DIFFERENTIAL SPLIT-LEVEL CMOS
Subjects: T Technology > TA Engineering (General). Civil engineering (General)
Divisions: Divisions > Division of Arts and Humanities > School of Arts
Depositing User: P. Ogbuji
Date Deposited: 27 Aug 2009 12:30 UTC
Last Modified: 16 Nov 2021 09:58 UTC
Resource URI: https://kar.kent.ac.uk/id/eprint/20366 (The current URI for this page, for reference purposes)

University of Kent Author Information

Waller, Winston A.J..

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