Testing Differential Split-Level CMOS Circuits

Aziz, S.M. and Waller, W.A.J (1994) Testing Differential Split-Level CMOS Circuits. Iee Proceedings-Circuits Devices and Systems, 141 (6). pp. 451-456. ISSN 1350-2409. (The full text of this publication is not available from this repository)

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Official URL
http://dx.doi.org/10.1049/ip-cds:19941524

Abstract

The paper addresses the problem of testing differential split-level (DSL) CMOS circuits. The behaviour of DSL circuits under single stuck-at, stuck-on and stuck-open faults is analysed. It is shown that most of these faults in DSL circuits cannot be deterministically tested by logic monitoring. However, the presence of any of these faults results in an increase in the steady state power supply current in the circuit when the fault is sensitised. A testing technique based on differential supply current monitoring to detect these faults in DSL integrated circuits is presented.

Item Type: Article
Uncontrolled keywords: TESTABILITY ANALYSIS; DESIGN FOR TESTABILITY; DIFFERENTIAL SPLIT-LEVEL CMOS
Subjects: T Technology > TA Engineering (General). Civil engineering (General)
Divisions: Faculties > Science Technology and Medical Studies > Centre for Music Technology
Depositing User: P. Ogbuji
Date Deposited: 27 Aug 2009 12:30
Last Modified: 09 Apr 2014 14:52
Resource URI: http://kar.kent.ac.uk/id/eprint/20366 (The current URI for this page, for reference purposes)
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