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Reducing Memory Bottlenecks in Embedded, Parallel Image Processors

McBader, Stephanie, Lee, Peter (2003) Reducing Memory Bottlenecks in Embedded, Parallel Image Processors. IEE Electronics Letters, 39 (1). pp. 33-35. ISSN 0013-5194. (doi:10.1049/el:20030020) (The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided) (KAR id:7622)

The full text of this publication is not currently available from this repository. You may be able to access a copy if URLs are provided.
Official URL:
http://dx.doi.org/10.1049/el:20030020

Abstract

Owing to the sequential nature of memory interfaces, as well as the growing processor-memory performance gap, the design of parallel image processors is often faced with a challenge in deciding memory organisation and distribution. This work addresses the problem of memory access bottlenecks in parallel digital image processors and presents one solution which demonstrates up to 93.4% reduction over standard sequential methods.

Item Type: Article
DOI/Identification number: 10.1049/el:20030020
Subjects: T Technology > TK Electrical engineering. Electronics. Nuclear engineering > TK7800 Electronics
Divisions: Divisions > Division of Computing, Engineering and Mathematical Sciences > School of Engineering and Digital Arts
Depositing User: Yiqing Liang
Date Deposited: 15 Sep 2008 10:22 UTC
Last Modified: 16 Nov 2021 09:45 UTC
Resource URI: https://kar.kent.ac.uk/id/eprint/7622 (The current URI for this page, for reference purposes)

University of Kent Author Information

Lee, Peter.

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