Double Precision Floating-Point Arithmetic on FPGAs

Paschalakis, S. and Lee, P. (2003) Double Precision Floating-Point Arithmetic on FPGAs. In: 2003 IEEE International Conference, Proceedings. IEEE Conference on Field-Programmable Technology (ICFPT 2003). IEEE, 345 E 47TH ST, New York, NY 10017 USA, USA pp. 352-358. ISBN 0-7803-8320-6 . (The full text of this publication is not available from this repository)

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Official URL
http://dx.doi.org/10.1109/FPT.2003.1275775

Abstract

We present low cost FPGA floating-point arithmetic circuits for all the common operations, i.e. addition/subtraction, multiplication, division and square root. Such circuits can be extremely useful in the FPGA implementation of complex systems that benefit from the reprogrammability and parallelism of the FPGA device but also require a general purpose arithmetic unit. While previous work has considered circuits for low precision floating-point formats, we consider the implementation of 64-bit double precision circuits that also provide rounding and exception handling.

Item Type: Conference or workshop item (Paper)
Uncontrolled keywords: There is no keyword written in the paper.
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800 Electronics (see also: telecommunications)
Divisions: Faculties > Science Technology and Medical Studies > School of Engineering and Digital Arts > Instrumentation, Control and Embedded Systems
Depositing User: Yiqing Liang
Date Deposited: 04 Aug 2009 08:33
Last Modified: 14 Jan 2010 14:28
Resource URI: http://kar.kent.ac.uk/id/eprint/7583 (The current URI for this page, for reference purposes)
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