Reconfigurable processing framework for space-time block codes

Space-time block coding has emerged in recent years as a promising research topic to enable future high-speed wireless communications networks and services. A considerable number of authors have developed algorithms and techniques that have been explored in simulations. However, fully implemented systems are rare. This paper considers the use of reconfigurable logic for implementing space-time block coding algorithms, allowing greater coding complexity than traditional DSP implemented systems. In particular, a number of matrix multiplication-style architectures are proposed for implementing channel estimators on FPGA hardware. These are compared in terms of speed and size, and accuracy is compared with a MATLAB simulation.

Reconfigurable processing framework for space-time block codes (PDF Download Available). Available from: http://www.researchgate.net/publication/228991771_Reconfigurable_processing_framework_for_space-time_block_codes [accessed Sep 4, 2015].