An FPGA based Digital Lock-In Amplifier Implemented using MFIR Resonators

This paper presents an alternative architecture for a digital lock-in amplifier that uses a linear phase digital low pass resonator built with a Multiplicative Finite Impulse Response (MFIR) filter. The paper compares the performance of the new architecture with traditional implementations that have been described in the literature. It shows that the MFIR resonator has a superior performance due to its very small equivalent noise bandwidth. The system has been implemented and tested on a Xilinx Spartan3A DSP Field Programmable Gate Array (FPGA). The paper also shows that the MFIR filter only uses a small amount of slices which makes it perfectly suited for implementation in state of the art mid-range FPGA’s.