Preventing Instantiation Errors and Loops for Logic Programs with Several Modes Using block Declarations

Smaus, Jan-Georg and Hill, Pat and King, Andy (1998) Preventing Instantiation Errors and Loops for Logic Programs with Several Modes Using block Declarations. In: Flener, Pierre, ed. Logic Programming, Synthesis and Transformation. Lecture Notes in Computer Science, 1559 . Springer, pp. 182-196. ISBN 3-540-65765-7. (Full text available)

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Abstract

We present verification methods for logic programs with delay declarations, showing how type and instantiation errors related to built-ins can be avoided, and how termination can be ensured. Three features are distinctive of this work: (a) we assume that predicates can be used in several modes; (b) we show that block declarations, which are a particularly simple delay construct, are sufficient to ensure the desired properties; (c) we take the selection rule into account, assuming it to be the rule of most Prolog implementations. These methods can be used both to verify existing programs and to assist in writing new programs.

Item Type: Book section
Additional information: Extended abstract. Accepted for presentation at the LOPSTR 98 workshop.
Uncontrolled keywords: Logic programing, delay declaration, block declaration, built-in, error, termination, mode
Subjects: Q Science > QA Mathematics (inc Computing science) > QA 76 Software, computer programming,
Divisions: Faculties > Science Technology and Medical Studies > School of Computing > Theoretical Computing Group
Depositing User: Andy King
Date Deposited: 07 Dec 2009 15:00
Last Modified: 15 Dec 2013 17:31
Resource URI: http://kar.kent.ac.uk/id/eprint/21649 (The current URI for this page, for reference purposes)
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