Hanna, Keith (1998) Automatic Verification of Mixed-Level Logic Circuits. In: Formal Methods in Computer-Aided Design.
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An approach is described to the specification and verification of digital systems implemented wholly or partly at the analog level of abstraction. The approach relies upon specifying the behaviours of analog components (such as transistors) by piecewise-linear predicates on voltages and currents. A decision procedure is described that can, for a wide class of specifications, automatically establish the correctness of an implementation.
|Item Type:||Conference or workshop item (Paper)|
|Subjects:||Q Science > QA Mathematics (inc Computing science) > QA 76 Software, computer programming,|
|Divisions:||Faculties > Science Technology and Medical Studies > School of Computing > Theoretical Computing Group|
|Depositing User:||Mark Wheadon|
|Date Deposited:||26 Aug 2009 18:05|
|Last Modified:||26 Aug 2009 18:05|
|Resource URI:||http://kar.kent.ac.uk/id/eprint/21573 (The current URI for this page, for reference purposes)|
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