Waller, W.A.J. and Aziz, S.M. (1994) A C-Testable Parallel Multipler Using Differencial Casecode Voltage Swish (DCVS) Logic. In: IFIP TC10/WG10.5 International Conference on Very Large Scale Integration (VLSI 93), Grenoble, France.
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In this paper, a new C-testable design of a parallel multiplier is presented. It is based on the well known modified Booth's algorithm which reduces the number of partial products by a factor of two compared to the straightforward iterative array multiplier. The multiplier is implemented using the highly testable clocked Differential Cascode Voltage Switch (DCVS) logic. It requires only 21 test vectors to detect all detectable single stuck-at, stuck-on and stuck-open faults. Compared to a non-C-testable DCVS design, it requires only 6 extra inputs, 2 extra outputs and a small amount of extra logic which is also self-checking.
|Item Type:||Conference or workshop item (Other)|
|Subjects:||Q Science > QA Mathematics (inc Computing science) > QA 75 Electronic computers. Computer science|
|Divisions:||Faculties > Science Technology and Medical Studies > School of Computing > Theoretical Computing Group|
|Depositing User:||P. Ogbuji|
|Date Deposited:||09 Jun 2009 16:51|
|Last Modified:||27 Jun 2012 10:29|
|Resource URI:||http://kar.kent.ac.uk/id/eprint/20093 (The current URI for this page, for reference purposes)|
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