Swenson, R.L. and Dimond, K.R. (1999) A hardware FPGA implementation of a 2-D median filter using a novel rank adjustment technique. In: 7th IEE Conference on Image Processing and its Applications (IPA99), Jul 12-15, 1999, Manchester, England.
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This paper presents the design and implementation on a Field Programmable Gate Array (FPGA) of a 2-D median filter, which is capable of obtaining a median value every clock cycle. The device is designed to operate in rear-time with rates of over 80 megasamples per second on n-bit sample sequences. Also, the operation speed remains constant regardless of the size of the selected mask N.
|Item Type:||Conference or workshop item (Paper)|
|Additional information:||Proceedings Paper; Issue: 465|
Q Science > Q Science (General) > Q335 Artificial intelligence
T Technology > TA Engineering (General). Civil engineering (General)
Q Science > QA Mathematics (inc Computing science) > QA 76 Software, computer programming,
|Divisions:||Faculties > Science Technology and Medical Studies > School of Engineering and Digital Arts|
|Depositing User:||F.D. Zabet|
|Date Deposited:||23 Mar 2009 18:09|
|Last Modified:||23 Mar 2009 18:09|
|Resource URI:||http://kar.kent.ac.uk/id/eprint/16659 (The current URI for this page, for reference purposes)|
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