Elsehely, E. and Sobhy, M.I (2000) Real time radar target detection under jamming conditions using wavelet transform on FPGA device. IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 4 . pp. 545-548.
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An Architecture and a prototype implementation of radar target detection under jamming condition are presented. This paper presents an implementation of the work presented in  on the field programmable gate array (FPGA). The algorithm designed in this paper is based on the multiresolution wavelet analysis, calculation of the wavelet maxima coefficients, integration of the maxima coefficients and identification of the target pulse edges from unwanted coefficients. The implementation occupies about 2500 configurable logic blocks on a Xilinx XC4000XLA family FPGA.
|Additional information:||Document Type: Proceedings Paper Conference Information: IEEE International Symposium on Circuits and Systems (ISCAS 2000) GENEVA, SWITZERLAND, MAY 28-31, 2000 IEEE Circuits & Syst Soc; Swiss Fed Inst Technol|
|Subjects:||T Technology > TK Electrical engineering. Electronics Nuclear engineering
Q Science > QA Mathematics (inc Computing science) > QA 75 Electronic computers. Computer science
|Divisions:||Faculties > Science Technology and Medical Studies > School of Computing|
|Depositing User:||O.O. Odanye|
|Date Deposited:||19 May 2009 19:49|
|Last Modified:||19 May 2009 19:49|
|Resource URI:||http://kar.kent.ac.uk/id/eprint/16067 (The current URI for this page, for reference purposes)|
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