An implementation of a multiplierless Hough transform on an FPGA platform using hybrid-log arithmetic

This paper describes an implementation of the Hough Transform (HT) that uses a hybrid-log structure for the main arithmetic components instead of fixed or floating point architectures. A major advantage of this approach is a reduction in the overall computational complexity of the HT without adversely affecting its overall performance when compared to fixed point solutions. The proposed architecture is compatible with the latest FPGA architectures allowing multiple units to operate in parallel without exhausting the dedicated (but limited) on-chip signal processing resources that can instead be allocated to other image processing and classification tasks. The solution proposed is capable of performing a realtime HT on megapixel images at frame rates of up to 25 frames per second using a Xilinx Virtex4 (TM) architecture.